1. Field
The present invention relates to the field of electroplating, and more particularly to the application of electroplating to the fabrication of interconnect structures in semiconductor devices.
2. Description of Related Art
One phenomenon that is observed during semiconductor fabrication electroplating is the formation of defects such as voids in the metallization. A significant number of voids will result in a detrimentally lowered conductivity of a metallization such as a contact as well as poor electromigration resistance. In some cases, the void or voids may be sufficiently large to cause an open circuit and the device fails. FIG. 1 illustrates a semiconductor structure 10 including a substrate with a recess 14 therein. In FIG. 1, the recess 14 corresponds to a trench or a via. A seed layer 16 is located at the bottom and on the sidewalls of the recess 14.
Each successive process generation results, in general, in a reduction in the critical dimensions (CDs) of the metal linewidths and via diameters. The aspect ratio of a feature (height: width) and the step coverage of the barrier/seed (B/S) represent some of the critical parameters of the upstream processes that may impact gapfill at copper electroplating (Cu EP). Lateral seed encroachment into the feature may be referred to as B/S overhang. An overhang 22, illustrated in FIG. 1, effectively increases the aspect ratio by reducing the width of the recess 14 at the top compared to the width of the recess 14 at the bottom, which may result in a center void 18 at the top of the feature. A sidewall void 20 may occur if the Cu seed coverage at a particular location is too thin or non-existent. The defects illustrated in FIG. 1 have been observed where a known Cu EP process was applied to trenches and vias characterized by widths of less than 100 nanometers (sub-100 nm trenches and vias). Thus, FIG. 1 demonstrates the gapfill capability of a known Cu EP process.
As miniaturization of device features continues to progress, the possibility of forming voids in Cu interconnects increases and the electroplating process must be improved or modified to ensure void free gapfill.